The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2008
Filed:
Mar. 15, 2005
Shih-ping Hsu, Hsin-chu, TW;
Sao-hsia Tang, Hsin-chu, TW;
Ying-tung Wang, Hsin-chu, TW;
Wen-hung HU, Hsin-chu, TW;
Chao-wen Shih, Hsin-chu, TW;
Meng-da Chou, Hsin-chu, TW;
Shih-Ping Hsu, Hsin-chu, TW;
Sao-Hsia Tang, Hsin-chu, TW;
Ying-Tung Wang, Hsin-chu, TW;
Wen-Hung Hu, Hsin-chu, TW;
Chao-Wen Shih, Hsin-chu, TW;
Meng-Da Chou, Hsin-chu, TW;
Phoenix Precision Technology Corporation, Hsin-chu, TW;
Abstract
A method for fabricating conductive bumps of a circuit board is proposed. First of all, a circuit board having a first surface and a corresponding second surface is provided. A circuit structure having a plurality of conductive pads is formed on each of the first surface and the second surface, and conductive structures are formed in the circuit board for electrically connecting the circuit structures. Also, an insulating layer having a plurality of openings penetrating therethrough is formed on the circuit board for exposing the conductive pad. Then, a conductive layer is formed on a surface of the insulating layer having the opening formed on the first surface of the circuit board. An electroplating process is performed via the conductive layer and the conductive structure, such that a conductive bump is formed on the conductive pad located on the second surface of the circuit board. Subsequently, a resist layer is formed on the second surface of the circuit board to cover the conductive bump, and another resist layer having openings penetrating therethrough is formed on the first surface of the circuit board to expose the conductive pad. Finally, a conductive bump is formed on the conductive pad located on the first surface of the circuit board by an electroplating process. By such arrangement, the conductive bumps are successively formed on the first surface and the second surface of the circuit board.