The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2008
Filed:
Jan. 31, 2006
Brian K. Kirkpatrick, Allen, TX (US);
Rajesh Khamankar, Coppell, TX (US);
Malcolm J. Bevan, Dallas, TX (US);
April Gurba, Plano, TX (US);
Husam N. Alshareef, Murphy, TX (US);
Clinton L. Montgomery, Coppell, TX (US);
Mark H. Somervell, Richardson, TX (US);
Brian K. Kirkpatrick, Allen, TX (US);
Rajesh Khamankar, Coppell, TX (US);
Malcolm J. Bevan, Dallas, TX (US);
April Gurba, Plano, TX (US);
Husam N. Alshareef, Murphy, TX (US);
Clinton L. Montgomery, Coppell, TX (US);
Mark H. Somervell, Richardson, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.