Lamellar-derived microelectronic component array and method of fabrication

Abstract

Sub-lithographic lamella and pillar structures defined by larger lines or lamellae are described. A static random access memory (SRAM) cell structure is created in a three-dimensional format as a vertical stack of wired transistors. These transistors are fabricated from crystalline silicon, and supplemental wiring structure features are fabricated to comprise a circuit along the walls of a vertical pillar. The three-dimensional cell integrated circuit can be created by a single mask step. Various structural features and methods of fabrication are described in detail. Peripheral interface, a two pillar version and other supplemental techniques and structural variations are also described.