The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2008
Filed:
Jun. 25, 2001
Takashi Nihonmatsu, Nagano, JP;
Masahiko Yoshida, Nagano, JP;
Yoshinori Sasaki, Nagano, JP;
Masahito Saitoh, Nagano, JP;
Toshiaki Takaku, Fukushima, JP;
Tadahiro Kato, Fukushima, JP;
Takashi Nihonmatsu, Nagano, JP;
Masahiko Yoshida, Nagano, JP;
Yoshinori Sasaki, Nagano, JP;
Masahito Saitoh, Nagano, JP;
Toshiaki Takaku, Fukushima, JP;
Tadahiro Kato, Fukushima, JP;
Shin-Etsu Handotai Co., Ltd., Tokyo, JP;
Abstract
There is provided a method for processing a semiconductor wafer subjected to a chamfering process, a lapping process, an etching process, and a mirror-polishing process, wherein acid etching is performed after alkaline etching as the etching process, and the acid etching is performed with an acid etchant composed of hydrofluoric acid, nitric acid, phosphoric acid, and water, a method for processing a semiconductor wafer subjected to a chamfering process, a surface grinding process, an etching process, and a mirror-polishing process, wherein the etching process is performed as described above, and a method for processing a semiconductor wafer subjected to a flattening process, an etching process, and a mirror-polishing process, wherein the etching process is performed as described above, a back surface polishing process is performed after the acid etching as the mirror-polishing process, and then a front surface polishing process is performed. According to this, there can be provided a method for processing a semiconductor wafer to have good flatness, good surface roughness, and good condition on a back surface thereof.