The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2008
Filed:
May. 25, 2004
Tetsuo Endoh, Natori, JP;
Fujio Masuoka, Sendai-shi, Miyagi, JP;
Shinji Horii, Kasaoka, JP;
Takuji Tanigami, Fukuyama, JP;
Yoshihisa Wada, Fukuyama, JP;
Takashi Yokoyama, Kasaoka, JP;
Noboru Takeuchi, Fukuyama, JP;
Tetsuo Endoh, Natori, JP;
Fujio Masuoka, Sendai-shi, Miyagi, JP;
Shinji Horii, Kasaoka, JP;
Takuji Tanigami, Fukuyama, JP;
Yoshihisa Wada, Fukuyama, JP;
Takashi Yokoyama, Kasaoka, JP;
Noboru Takeuchi, Fukuyama, JP;
Other;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
The present invention provides a semiconductor memory device having one or more protruding semiconductor layers formed on a semiconductor substrate of a first conductivity type and a plurality of memory cells on surfaces of the protruding semiconductor layers, wherein each of the memory cells is formed of a charge storage layer, a control gate and an impurity diffusion layer of a second conductivity type which is formed in a portion of the protruding semiconductor layer and the plurality of memory cells is aligned to at least a predetermined direction, and the control gates of the plurality of memory cells is aligned to the predetermined direction are placed so as to be separated from each other.