The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2007
Filed:
Mar. 01, 2004
Todd P. Lukanc, San Jose, CA (US);
Cyrus E. Tabery, Santa Clara, CA (US);
Luigi Capodieci, Santa Cruz, CA (US);
Carl Babcock, Campbell, CA (US);
Hung-eil Kim, San Jose, CA (US);
Christopher A. Spence, Sunnyvale, CA (US);
Chris Haidinyak, Santa Cruz, CA (US);
Todd P. Lukanc, San Jose, CA (US);
Cyrus E. Tabery, Santa Clara, CA (US);
Luigi Capodieci, Santa Cruz, CA (US);
Carl Babcock, Campbell, CA (US);
Hung-Eil Kim, San Jose, CA (US);
Christopher A. Spence, Sunnyvale, CA (US);
Chris Haidinyak, Santa Cruz, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.