The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2007
Filed:
Mar. 09, 2004
Dana Lee, Santa Clara, CA (US);
Bomy Chen, Cupertino, CA (US);
Sohrab Kianian, Los Altos Hills, CA (US);
Dana Lee, Santa Clara, CA (US);
Bomy Chen, Cupertino, CA (US);
Sohrab Kianian, Los Altos Hills, CA (US);
Silicon Storage Technology, Inc., Sunnyvale, CA (US);
Abstract
A buried bit line read/program non-volatile memory cell and array is capable of achieving high density. The cell and array is made in a semiconductor substrate which has a plurality of spaced apart trenches, with a planar surface between the trenches. Each trench has a side wall and a bottom wall. Each memory cell has a floating gate for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having two portions. One of the source/drain regions is in the bottom wall of the trench. The floating gate is in the trench and is is over a first portion of the channel and is spaced apart from the side wall of the trench. A gate electrode controls the conduction of the channel in the second portion, which is in the planar surface of the substrate. The other source/drain region is in the substrate in the planar surface of the substrate. An independently controllable control gate is also in the trench, insulated from the floating gate and is capacitively coupled thereto. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode or from the floating gate to the source/drain region at the bottom wall of the trench. The source, drain and control gates are all substantially parallel to one another, with the gate electrode substantially perpendicular to the source/drain/control gates. The source/drain lines are buried in the substrate, creating a virtual ground array.