The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2007

Filed:

Oct. 29, 2004
Applicants:

Jin-wook Jeong, Ichon-si, KR;

In-sang Yoon, Ichon-si, KR;

Hee Bong Lee, Ichon-si, KR;

Hyun-joon OH, Austin, TX (US);

Hyeog Chan Kwon, Seoul, KR;

Jong Wook Ju, Kyoungnam, KR;

Sang Ho Lee, Kyonggi, KR;

Inventors:

Jin-Wook Jeong, Ichon-si, KR;

In-Sang Yoon, Ichon-si, KR;

Hee Bong Lee, Ichon-si, KR;

Hyun-Joon Oh, Austin, TX (US);

Hyeog Chan Kwon, Seoul, KR;

Jong Wook Ju, Kyoungnam, KR;

Sang Ho Lee, Kyonggi, KR;

Assignee:

Chippac Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

Individual pieces of film adhesive () are placed on a support surface (). Diced semiconductor chips () are individually placed on the individual pieces of the film adhesive thereby securing the diced semiconductor chips to the support surface to create first chip subassemblies (). The diced semiconductor chip and support surface of each of a plurality of the first chip subassemblies are electrically connected, such as by wires (), to create second chip subassemblies ((). At least a portion of at least some of the second chip subassemblies are encapsulated, such as with molding compound (), to create semiconductor chip packages ().


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