The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2007
Filed:
Nov. 04, 2005
Tetsuo Adachi, Ome, JP;
Masataka Kato, Koganei, JP;
Toshiaki Nishimoto, Higashimurayama, JP;
Nozomu Matsuzaki, Kokubunji, JP;
Takashi Kobayashi, Tokorozawa, JP;
Yoshimi Sudou, Akiruno, JP;
Toshiyuki Mine, Fussa, JP;
Tetsuo Adachi, Ome, JP;
Masataka Kato, Koganei, JP;
Toshiaki Nishimoto, Higashimurayama, JP;
Nozomu Matsuzaki, Kokubunji, JP;
Takashi Kobayashi, Tokorozawa, JP;
Yoshimi Sudou, Akiruno, JP;
Toshiyuki Mine, Fussa, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.