Self-aligned sti sonos

Abstract

Methodsandare disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspectcomprises forminga multi-layer dielectric-charge trapping-dielectric stackover a substrateof the wafer, for example, an ONO stack, removingthe multi-layer dielectric-charge trapping-dielectric stackin a periphery regionof the wafer, thereby defining a multi-layer dielectric-charge trapping-dielectric stackin a core regionof the wafer. The methodfurther comprises forminga gate dielectric layerover the periphery regionof the substrate, forminga first polysilicon layerover the multi-layer dielectric-charge trapping-dielectric stackin the core regionand the gate dielectricin the periphery region, then concurrently formingan isolation trenchin the substratein the core regionand in the periphery region. Thereafter, the isolation trenches are filledwith a dielectric material, and a second polysilicon layerthat is formedover the first polysilicon layerand the filled trenches, forming an self-aligned STI structure. The methodavoids ONO residual stringers at STI edges in the periphery region, reduces active region losses, reduces thinning of the periphery gate oxide and the ONO at the STI edge, and reduces dopant diffusion during isolation implantations due to reduced thermal process steps.