The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2007
Filed:
Jan. 26, 2006
Jen-shou Hsu, Hsinchu, TW;
Tah-kang Joseph Ting, Hsinchu, TW;
Ming-hung Wang, Hsinchu, TW;
Bor-doou Rong, Hsinchu, TW;
Jen-Shou Hsu, Hsinchu, TW;
Tah-Kang Joseph Ting, Hsinchu, TW;
Ming-Hung Wang, Hsinchu, TW;
Bor-Doou Rong, Hsinchu, TW;
Etron Technology Inc., Hsinchu, TW;
Abstract
A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.