The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 2007
Filed:
Nov. 01, 2004
Diane C. Boyd, LaGrangeville, NY (US);
Juan Cai, Freemont, CA (US);
Kevin K. Chan, Staten Island, NY (US);
Patricia M. Mooney, Mount Kisco, NY (US);
Kern Rim, Yorktown Heights, NY (US);
Diane C. Boyd, LaGrangeville, NY (US);
Juan Cai, Freemont, CA (US);
Kevin K. Chan, Staten Island, NY (US);
Patricia M. Mooney, Mount Kisco, NY (US);
Kern Rim, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.