The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2007
Filed:
Feb. 08, 2006
Luverne Peterson, San Diego, CA (US);
Jonathan A. Levi, Fallbrook, CA (US);
Paul Abelovski, Escondido, CA (US);
Roger Mar, San Diego, CA (US);
LuVerne Peterson, San Diego, CA (US);
Jonathan A. Levi, Fallbrook, CA (US);
Paul Abelovski, Escondido, CA (US);
Roger Mar, San Diego, CA (US);
Toshiba America Electronic Components, Inc., San Diego, CA (US);
Abstract
A generalized method for testing DACs (Digital to Analog Converters) and ADCs (Analog to Digital Converters), such as Sigma Delta (Successive Approximation), Pipeline or Flash ADCs. The DACs and ADCs are tested in pairs using a Digital Tester and on chip test circuitry. The DACs and ADCs may be tested at the highest clock frequency allowed in the specification, shortening test time. The test circuits required for this test scheme comprise cell logic two multiplexer cells and an internal Analog Test Bus. This scheme is extendable to the testing of many DACs and ADCs on the same IC. The number of DACs and ADCs need not be equal. Furthermore, the DACs may have more (or less) bits (addresses) than the ADCs. An ADC may be tested with more than one DAC or vice versa to determine which cell is at fault if a test fails.