The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2007
Filed:
Dec. 10, 2004
Lois E. Yong, Austin, TX (US);
Peter R. Harper, Round Rock, TX (US);
Tu Anh Tran, Austin, TX (US);
Jeffrey W. Metz, Round Rock, TX (US);
George R. Leal, Cedar Park, TX (US);
Dieu Van Dinh, Austin, TX (US);
Lois E. Yong, Austin, TX (US);
Peter R. Harper, Round Rock, TX (US);
Tu Anh Tran, Austin, TX (US);
Jeffrey W. Metz, Round Rock, TX (US);
George R. Leal, Cedar Park, TX (US);
Dieu Van Dinh, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A bond pad () has a probe region () and a wire bond region () that are substantially non-overlapping. In one embodiment, the bond pad () is connected to a final metal layer pad () and extends over an interconnect region (). The bond pad () is formed from aluminum and the final metal layer pad () is formed from copper. Separating the probe region () from the wire bond region () prevents the final metal layer pad () from being damaged by probe testing, allowing for more reliable wire bonds. In another embodiment, the probe region () extends over a passivation layer (). In an application requiring very fine pitch between bond pads, the probe regions () and wire bond regions () of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (). In addition, forming the bond pads () over the interconnect region () reduces the size of the integrated circuit.