The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2007
Filed:
Apr. 02, 2004
Cyrus E. Tabery, Santa Clara, CA (US);
Todd P. Lukanc, San Jose, CA (US);
Chris Haidinyak, Santa Cruz, CA (US);
Luigi Capodieci, Santa Cruz, CA (US);
Carl P. Babcock, Campbell, CA (US);
Hung-eil Kim, San Jose, CA (US);
Christopher A. Spence, Sunnyvale, CA (US);
Cyrus E. Tabery, Santa Clara, CA (US);
Todd P. Lukanc, San Jose, CA (US);
Chris Haidinyak, Santa Cruz, CA (US);
Luigi Capodieci, Santa Cruz, CA (US);
Carl P. Babcock, Campbell, CA (US);
Hung-eil Kim, San Jose, CA (US);
Christopher A. Spence, Sunnyvale, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).