The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2007
Filed:
Aug. 10, 2004
Bang-chien Ho, Hsin-Chu, TW;
Jian-hong Chen, Hsin-Chu, TW;
Tsang-jiuh Wu, Taichung, TW;
Li-te Lin, Hsin-Chu, TW;
Li-chih Chao, Tao-Yuan, TW;
Hua-tai Lin, Yu-Kang, TW;
Shyue-sheng LU, Hsin-Chu, TW;
Bang-Chien Ho, Hsin-Chu, TW;
Jian-Hong Chen, Hsin-Chu, TW;
Tsang-Jiuh Wu, Taichung, TW;
Li-Te Lin, Hsin-Chu, TW;
Li-Chih Chao, Tao-Yuan, TW;
Hua-Tai Lin, Yu-Kang, TW;
Shyue-Sheng Lu, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.