The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2007
Filed:
May. 20, 2005
Feng Gao, Sunnyvale, CA (US);
Ya-fen Lin, Santa Clara, CA (US);
John W. Cooksey, Brentwood, CA (US);
Changyuan Chen, Sunnyvale, CA (US);
Yuniarto Widjaja, San Jose, CA (US);
Dana Lee, Santa Clara, CA (US);
Feng Gao, Sunnyvale, CA (US);
Ya-Fen Lin, Santa Clara, CA (US);
John W. Cooksey, Brentwood, CA (US);
Changyuan Chen, Sunnyvale, CA (US);
Yuniarto Widjaja, San Jose, CA (US);
Dana Lee, Santa Clara, CA (US);
Silicon Storage Technology, Inc., Sunnyvale, CA (US);
Abstract
A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.