The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2007
Filed:
Jul. 29, 2004
PR Chidambaram, Richardson, TX (US);
Douglas T. Grider, McKinney, TX (US);
Brian A. Smith, Plano, TX (US);
Haowen Bu, Plano, TX (US);
Lindsey Hall, Plano, TX (US);
Pr Chidambaram, Richardson, TX (US);
Douglas T. Grider, McKinney, TX (US);
Brian A. Smith, Plano, TX (US);
Haowen Bu, Plano, TX (US);
Lindsey Hall, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method () of forming a transistor includes forming a gate structure () over a semiconductor body and forming recesses () substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown () in the recesses, followed by forming sidewall spacers () over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body () after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.