The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2007

Filed:

Sep. 13, 2005
Applicants:

Muhammad M. Khellah, Tigard, OR (US);

Dinesh Somasekhar, Portland, OR (US);

Nam Sung Kim, Hillsboro, OR (US);

Yibin YE, Portland, OR (US);

Vivek K. DE, Beaverton, OR (US);

Kevin Zhang, Portland, OR (US);

BO Zheng, Portland, OR (US);

Inventors:

Muhammad M. Khellah, Tigard, OR (US);

Dinesh Somasekhar, Portland, OR (US);

Nam Sung Kim, Hillsboro, OR (US);

Yibin Ye, Portland, OR (US);

Vivek K. De, Beaverton, OR (US);

Kevin Zhang, Portland, OR (US);

Bo Zheng, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.


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