The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2007
Filed:
Oct. 01, 2004
Sakae Koyata, Tokyo, JP;
Kazushige Takaishi, Tokyo, JP;
Tohru Taniguchi, Tokyo, JP;
Kazuo Fujimaki, Tokyo, JP;
Akihiro Kudo, Tokyo, JP;
Masashi Norimoto, Tokyo, JP;
Sakae Koyata, Tokyo, JP;
Kazushige Takaishi, Tokyo, JP;
Tohru Taniguchi, Tokyo, JP;
Kazuo Fujimaki, Tokyo, JP;
Akihiro Kudo, Tokyo, JP;
Masashi Norimoto, Tokyo, JP;
Sumitomo Mitsubishi Silicon Corporation, Minato-ku, Tokyo, JP;
Abstract
Provided is an improved method for producing a silicon wafer whose surfaces exhibit precise flatness and minute surface roughness, and which allows one to visually discriminate between the front and rear surfaces, the method comprising a slicing step of slicing a single-crystal ingot into thin disc-like wafers, a chamfering step of chamfering the wafer, a lapping step for flattening the wafer, an etching step for removing processing distortions on the wafer surfaces, a mirror-polishing step for mirror-polishing the surface of the wafer, and a cleaning step for cleaning the wafer. The etching step further comprises a first acid-etching phase and a second alkali-etching phase, and a rear surface mild polishing step is introduced between the first and second etching phases in order to abrade part of roughness formed on the rear surface of the wafer as a result of the first etching phase.