The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2007

Filed:

Dec. 07, 2004
Applicants:

Chang Bum Kim, St. Louis, MO (US);

Steven L. Kimbel, St. Charles, MO (US);

Jeffrey L. Libbert, O'Fallon, MO (US);

Mohsen Banan, Grover, MO (US);

Inventors:

Chang Bum Kim, St. Louis, MO (US);

Steven L. Kimbel, St. Charles, MO (US);

Jeffrey L. Libbert, O'Fallon, MO (US);

Mohsen Banan, Grover, MO (US);

Assignee:

MEMC Electronics Materials, Inc., St. Peters, MO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C03B 15/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a process for preparing a single crystal silicon ingot, as well as to the ingot or wafer resulting therefrom. The process comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G, and (iii) a cooling rate of the crystal from solidification to about 750° C., in order to cause the formation of a segment having a first axially symmetric region extending radially inward from the lateral surface of the ingot wherein silicon self-interstitials are the predominant intrinsic point defect, and a second axially symmetric region extending radially inward from the first and toward the central axis of the ingot. The process is characterized in that v, Gand the cooling rate are controlled to prevent the formation of agglomerated intrinsic point defects in the first region, while the cooling rate is further controlled to limit the formation of oxidation induced stacking faults in a wafer derived from this segment, upon subjecting the wafer to an oxidation treatment otherwise suitable for the formation of such faults.


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