The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2007
Filed:
Apr. 05, 2005
Sangwoo Lim, Austin, TX (US);
Paul A. Grudowski, Austin, TX (US);
Mohamad M. Jahanbani, Austin, TX (US);
Hsing H. Tseng, Austin, TX (US);
Choh-fei Yeap, Austin, TX (US);
Sangwoo Lim, Austin, TX (US);
Paul A. Grudowski, Austin, TX (US);
Mohamad M. Jahanbani, Austin, TX (US);
Hsing H. Tseng, Austin, TX (US);
Choh-Fei Yeap, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer may be formed over the first gate dielectric layer after etching the portion. The second gate dielectric layer can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer. Subsequent gate electrode and source/drain region formation can be performed to form a transistor structure.