The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2007

Filed:

Jan. 19, 2005
Applicants:

Sung Jin Yang, Gangnam-gu, KR;

Doo Hwan Moon, Gwangjin-gu, KR;

Won Dai Shin, Gwanak-gu, KR;

Inventors:

Sung Jin Yang, Gangnam-gu, KR;

Doo Hwan Moon, Gwangjin-gu, KR;

Won Dai Shin, Gwanak-gu, KR;

Assignee:

Amkor Technology, Inc., Chandler, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01B 13/00 (2006.01); C23F 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In accordance with the present invention, there is provided a method for manufacturing a semiconductor package. The method comprises the initial step of applying first and second photoresist layers to respective ones of opposed first and second surfaces of a metal plate which includes a die paddle and a plurality of leads extending at least partially about the die paddle in spaced relation thereto. The first and second photoresist layers are then patterned to expose the die paddle and prescribed portions of each of the leads. Thereafter, first and second conductive layers are applied to portions of respective ones of the first and second surfaces which are not covered by the first and second photoresist layers. The first and second photoresist layers are then removed to facilitate the creation of an exposed area in each of leads which is not covered by the first and second conductive layers. Next, a semiconductor die is attached to a portion of the first conductive layer covering the die paddle and electrically connected to portions of the first conductive layer covering the leads. The semiconductor die, the die paddle, the leads and the first and second conductive layers are then encapsulated with a package body such that portions of the second conductive layer covering the die paddle and the leads, and the exposed area of each of the leads are exposed in a common surface of the package body. Finally, the exposed area of each of the leads is etched to facilitate the division of the leads into an inner set extending at least partially about the die paddle and an outer set extending at least partially about the inner set.


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