Method for performing atpg and fault simulation in a scan-based integrated circuit

Abstract

A method for performing ATPG (automatic test pattern generation) and fault simulation in a scan-based integrated circuit, based on a selected clock order in a selected capture operation, in a selected scan-test mode or a selected self-test mode. The method comprises compilingthe RTL (register-transfer level) or Gate-Level HDL (hardware description language) codebased on the Input Constraintsand a Foundry Library, into a Sequential Circuit Model. The Sequential Circuit Modelis then transformedinto an equivalent Combinational Circuit Modelfor performing Forward and/or Backward Clock Analysisto determine the driving and observing clocks for all inputs and outputs of all combinational logic gates in the Combinational Circuit Model. The analysis results are used for Uncontrollable/Unobservable Labelingof selected inputs and outputs of the combinational logic gates. Finally, ATPG and/or Fault Simulationare performed according to the Uncontrollable/Unobservable Labelingto generate the HDL Test Benches and ATE Test Programs