The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2007

Filed:

Sep. 14, 2006
Applicants:

Bomy Chen, Cupertino, CA (US);

Sohrab Kianian, Los Altos Hills, CA (US);

Jack Frayer, Boulder Creek, CA (US);

Inventors:

Bomy Chen, Cupertino, CA (US);

Sohrab Kianian, Los Altos Hills, CA (US);

Jack Frayer, Boulder Creek, CA (US);

Assignee:

Silicon Storage Technology, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/336 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. An independently controllable control gate is insulated from each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. The independently controllable control gates permit an array of such memory cells to operate in a NAND configuration.


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