The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 03, 2007
Filed:
Mar. 29, 2004
Chih-ta Wu, Hsinchu, TW;
Kuo-yin Lin, Taichung, TW;
Tsung-hsun Huang, Taipei, TW;
Chung-yi Yu, Hsin-Chu, TW;
Lan-lin Chao, Sindian, TW;
Yeur-luen Tu, Taichung, TW;
Hsing-lien Lin, Hsin-Chu, TW;
Chia-shiung Tsai, Hsin-Chu, TW;
Chih-Ta Wu, Hsinchu, TW;
Kuo-Yin Lin, Taichung, TW;
Tsung-Hsun Huang, Taipei, TW;
Chung-Yi Yu, Hsin-Chu, TW;
Lan-Lin Chao, Sindian, TW;
Yeur-Luen Tu, Taichung, TW;
Hsing-Lien Lin, Hsin-Chu, TW;
Chia-Shiung Tsai, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.