The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2007
Filed:
Apr. 02, 2004
Todd P. Lukanc, San Jose, CA (US);
Cyrus E. Tabery, Santa Clara, CA (US);
Luigi Capodieci, Santa Cruz, CA (US);
Carl Babcock, Campbell, CA (US);
Hung-eil Kim, San Jose, CA (US);
Christopher A. Spence, Sunnyvale, CA (US);
Chris Haidinyak, Santa Cruz, CA (US);
Todd P. Lukanc, San Jose, CA (US);
Cyrus E. Tabery, Santa Clara, CA (US);
Luigi Capodieci, Santa Cruz, CA (US);
Carl Babcock, Campbell, CA (US);
Hung-eil Kim, San Jose, CA (US);
Christopher A. Spence, Sunnyvale, CA (US);
Chris Haidinyak, Santa Cruz, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules can be created to disallow layouts demonstrating poor manufacturability.