The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2007

Filed:

May. 20, 2004
Applicants:

Hiroyuki Ohta, Tsuchiura, JP;

Yukihiro Kumagai, Chiyoda, JP;

Masahiro Moniwa, Itami, JP;

Shingo Nasu, Chiyoda, JP;

Inventors:

Hiroyuki Ohta, Tsuchiura, JP;

Yukihiro Kumagai, Chiyoda, JP;

Masahiro Moniwa, Itami, JP;

Shingo Nasu, Chiyoda, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device which, even when a vertical transistor is adopted, is able to prevent a product yield from decreasing and performance from deteriorating, and at the same time, to achieve high-density integration of chips and high performance. The semiconductor device includes: a semiconductor substrate; a tower-like gate pillar formed on the semiconductor substrate via an insulation layer and including a channel region formed so as to be positioned between impurity diffusion regions in a vertically extended direction with respect to a principal side of the substrate; a gate insulation film formed on an outer surface of the gate pillar; and a gate electrode film including multiple conductive layers formed on an outer surface of the gate insulation film.


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