The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2007
Filed:
Jun. 25, 2002
Norihiro Kobayashi, Gunma, JP;
Masaro Tamatsuka, Gunma, JP;
Takatoshi Nagoya, Gunma, JP;
Wei Feig Qu, Gunma, JP;
Hiroshi Takeno, Gunma, JP;
Ken Aihara, Gunma, JP;
Norihiro Kobayashi, Gunma, JP;
Masaro Tamatsuka, Gunma, JP;
Takatoshi Nagoya, Gunma, JP;
Wei Feig Qu, Gunma, JP;
Hiroshi Takeno, Gunma, JP;
Ken Aihara, Gunma, JP;
Shin-Etsu Handotai Co., Ltd., Tokyo, JP;
Abstract
The present invention is a method of producing an annealed wafer wherein a silicon single crystal wafer having a diameter of 200 mm or more produced by the Czochralski (CZ) method is subjected to a high temperature heat treatment in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100–1350° C. for 10–600 minutes, and before the high temperature heat treatmen, a pre-annealing is performed at a temperature less than the temperature of the high temperature heat treatment, so that the growth of slip dislocations is suppressed by growing oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein the generation and growth of slip dislocations generated in a high temperature heat treatment are suppressed and the defect density in the wafer surface layer is lowered even in the case of a silicon single crystal wafer having a large diameter of 200 mm or more, and the annealed wafer.