The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2007

Filed:

Jun. 18, 2004
Applicants:

Jaime A. Bayan, Palo Alto, CA (US);

Santhiran S/o Nadarajah, Melaka, MY;

Chan Chee Ling, Negeri Sembilan, MY;

Ashok S. Prabhu, San Jose, CA (US);

Hasfiza Ramley, Cheras, MY;

Chan Peng Yeen, Melaka, MY;

Inventors:

Jaime A. Bayan, Palo Alto, CA (US);

Santhiran S/O Nadarajah, Melaka, MY;

Chan Chee Ling, Negeri Sembilan, MY;

Ashok S. Prabhu, San Jose, CA (US);

Hasfiza Ramley, Cheras, MY;

Chan Peng Yeen, Melaka, MY;

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a micro-array IC package is recited. A wafer has a B-stageable adhesive applied, and the wafer is diced. The individual dice are applied to a lead-frame via their adhesive, and wirebonded to associated leads. The lead-frame is then encapsulated, and solder connectors are applied. The lead-frame is then singulated to produce a plurality of lead-frame based micro-array packages. The process thus allows lead-frame based manufacturing methods to be employed in the production of BGA-type packages, allowing such packages to be produced faster and more efficiently.


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