The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2007
Filed:
Jan. 19, 2005
In-wook Cho, Yongin-si, KR;
Geum-jong Bae, Incheon-si, KR;
Ki-chul Kim, Suwon-si, KR;
Byoung-jin Lee, Seoul, KR;
Jin-hee Kim, Seongnam-si, KR;
Byou-ree Lim, Yongin-si, KR;
Sang-su Kim, Suwon-si, KR;
In-Wook Cho, Yongin-si, KR;
Geum-Jong Bae, Incheon-si, KR;
Ki-Chul Kim, Suwon-si, KR;
Byoung-Jin Lee, Seoul, KR;
Jin-Hee Kim, Seongnam-si, KR;
Byou-Ree Lim, Yongin-si, KR;
Sang-Su Kim, Suwon-si, KR;
Abstract
A nonvolatile memory cell array having common drain lines and method of operating the same are disclosed. A positive voltage is applied to a gate of a selected cell and gates of memory cells that share a word line with the selected cell. A first voltage is applied to a drain of the selected cell and drains of the memory cells that share at least a drain line with the selected cell. A second voltage is applied to a source of the selected cell and sources of memory cells that share a bit line with the selected cell, the second voltage being less than the first voltage, such that electrons are injected into the charge storage region of the selected cell to program. A third voltage, which is higher than the second voltage, is applied to bit lines that are not connected to the selected cell.