The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2007
Filed:
Dec. 17, 2002
Cheng Siew Tay, Penang, MY;
Swee Kian Cheng, Kedah, MY;
Eng Huat Goh, Penang, MY;
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric defined interconnect ratio of substrates. In addition selective orientation of the dielectric defined edge portion of the electrical interconnect away from the point where cracks initiate resists crack propagation and component failure.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile