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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7169674 B1

PDFFull Text
Date of Patent:
Jan. 30, 2007

Filed:

Feb. 28, 2005

Complementary metal oxide semiconductor (cmos) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier

Applicants:

Nestor Alexander Bojarczuk, Jr., Poughkeepsie, NY (US);

Kevin Kok Chan, Staten Island, NY (US);

Christopher Peter D'emic, Ossining, NY (US);

Evgeni Gousev, Mahopac, NY (US);

Supratik Guha, Chappaqua, NY (US);

Paul C. Jamison, Hopewell Junction, NY (US);

Lars-ake Ragnarsson, New York, NY (US);

Inventors:

Nestor Alexander Bojarczuk, Jr., Poughkeepsie, NY (US);

Kevin Kok Chan, Staten Island, NY (US);

Christopher Peter D'Emic, Ossining, NY (US);

Evgeni Gousev, Mahopac, NY (US);

Supratik Guha, Chappaqua, NY (US);

Paul C. Jamison, Hopewell Junction, NY (US);

Lars-Ake Ragnarsson, New York, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Stephen C. Kaufman, Esq.

McGinn IP Law Group, PLLC

Primary Examiner:

Michael Lebentritt

Assistant Examiner:

Mohsen Ahmadi

Int. Cl.
CPC ...
H01L 21/8236 (2006.01); H01L 21/8222 (2006.01); H01L 21/335 (2006.01); H01L 21/8234 (2006.01); H01L 21/336 (2006.01); H01L 21/331 (2006.01);
U.S. Cl.
CPC ...
Abstract

A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.

Find Patent Forward Citations

Bojarczuk, Jr., Nestor. (2007). Complementary metal oxide semiconductor (cmos) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier (U.S. Patent No. 7169674). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7169674

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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