The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2007
Filed:
Aug. 11, 2004
Hyungjun Park, Paju-Si, KR;
Hyeongno Kim, Paju-Si, KR;
Sangbae Park, Paju-Si, KR;
Yonggil Lee, Paju-Si, KR;
Kyungsoo Rho, Paju-Si, KR;
Junyoung Yang, Paju-Si, KR;
Jinhee Won, Paju-Si, KR;
HyungJun Park, Paju-Si, KR;
HyeongNo Kim, Paju-Si, KR;
SangBae Park, Paju-Si, KR;
YongGil Lee, Paju-Si, KR;
KyungSoo Rho, Paju-Si, KR;
JunYoung Yang, Paju-Si, KR;
JinHee Won, Paju-Si, KR;
Advanced Semiconductor Engineering, Inc., Kaosiung, TW;
Abstract
A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.