The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2007

Filed:

Apr. 19, 2005
Applicants:

Anil K. Chinthakindi, Wappingers Falls, NY (US);

Lawrence A. Clevenger, LaGrangeville, NY (US);

Tom C. Lee, Essex Junction, VT (US);

Gerald Matusiewicz, Poughkeepsie, NY (US);

Conal E. Murray, Yorktown Heights, NY (US);

Chih-chao Yang, Poughkeepsie, NY (US);

Inventors:

Anil K. Chinthakindi, Wappingers Falls, NY (US);

Lawrence A. Clevenger, LaGrangeville, NY (US);

Tom C. Lee, Essex Junction, VT (US);

Gerald Matusiewicz, Poughkeepsie, NY (US);

Conal E. Murray, Yorktown Heights, NY (US);

Chih-Chao Yang, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

A structure and method are disclosed for heat dissipation relative to a heat generating element in a semiconductor device. The structure includes a plurality of heat transmitting lines partially vertically coincidental with the heat generating element, and at least one interconnecting path from each heat transmitting line to a substrate of the semiconductor device. In one embodiment, the heat generating element includes a resistor in a non-first metal level. The invention is compatible with conventional BEOL interconnect schemes, minimizes the amount of heat transfer from the resistor to the surrounding interconnect wiring, thus eliminating the loss of current carrying capability in the wiring.


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