The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2007
Filed:
Mar. 19, 2004
Bradley O. Stimson, San Jose, CA (US);
Mitsuhiro Kaburaki, Narita, JP;
John C. Forster, San Francisco, CA (US);
Eric Delaurentis, Boulder Creek, CA (US);
Praburam Gopalraja, Sunnyvale, CA (US);
Patricia Rodriguez, Santa Clara, CA (US);
Anantha Subramani, San Jose, CA (US);
Bradley O. Stimson, San Jose, CA (US);
Mitsuhiro Kaburaki, Narita, JP;
John C. Forster, San Francisco, CA (US);
Eric Delaurentis, Boulder Creek, CA (US);
Praburam Gopalraja, Sunnyvale, CA (US);
Patricia Rodriguez, Santa Clara, CA (US);
Anantha Subramani, San Jose, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Apparatus for supporting a substrate such as a semiconductor wafer in a process chamber to improve power coupling through the substrate. The apparatus contains a pedestal assembly and a pedestal cover positioned over the top surface of and circumscribing the pedestal assembly for electrically isolating the pedestal assembly. The pedestal cover reduces conductive film growth in the wafer process region. As such, RF wafer biasing power from the pedestal assembly remains coupled through the substrate during processing.