The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2007
Filed:
Nov. 12, 2002
Cindy W. Chen, San Jose, CA (US);
Eddie Chiu, Pleasanton, CA (US);
Mavis J. Chaboya, San Jose, CA (US);
Yuh-jia Su, Cupertino, CA (US);
Cindy W. Chen, San Jose, CA (US);
Eddie Chiu, Pleasanton, CA (US);
Mavis J. Chaboya, San Jose, CA (US);
Yuh-Jia Su, Cupertino, CA (US);
Novellus Systems, Inc., San Jose, CA (US);
Abstract
A method is disclosed for removing a polysilicon layer from a semiconductor wafer, in which a downstream plasma source is used first to planarize the wafer, removing contours in the polysilicon layer caused by deposition over lithographic features, such as via holes. The planarizing process is followed by exposure to a plasma made by a direct, radio frequency plasma source, which may be in combination with the downstream plasma source, to perform the bulk etching of the polysilicon. The invention can produce planar surface topography after the top layer of the film is removed, in which the residual recess height of the polysilicon plug filling a via hole is less than about about 10 nm.