The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2006
Filed:
May. 04, 2004
Jeffrey P. Patton, Santa Clara, CA (US);
Austin C. Frenkel, San Jose, CA (US);
Thorsten Kammler, Ottendorft-Okrilla, DE;
Robert J. Chiu, San Jose, CA (US);
Errol Todd Ryan, Wappingers Falls, NY (US);
Darin A. Chan, San Francisco, CA (US);
Paul R. Besser, Sunnyvale, CA (US);
Paul L. King, Mountain View, CA (US);
Minh Van Ngo, Fremont, CA (US);
Jeffrey P. Patton, Santa Clara, CA (US);
Austin C. Frenkel, San Jose, CA (US);
Thorsten Kammler, Ottendorft-Okrilla, DE;
Robert J. Chiu, San Jose, CA (US);
Errol Todd Ryan, Wappingers Falls, NY (US);
Darin A. Chan, San Francisco, CA (US);
Paul R. Besser, Sunnyvale, CA (US);
Paul L. King, Mountain View, CA (US);
Minh Van Ngo, Fremont, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.