The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2006
Filed:
Jan. 21, 2005
Soon-bum Kim, Suwon-si, KR;
Ung-kwang Kim, Yongin-si, KR;
Kang-wook Lee, Suwon-si, KR;
Se-young Jeong, Seoul, KR;
Young-hee Song, Yongin-si, KR;
Sung-min Sim, Seongnam-si, KR;
Soon-Bum Kim, Suwon-si, KR;
Ung-Kwang Kim, Yongin-si, KR;
Kang-Wook Lee, Suwon-si, KR;
Se-Young Jeong, Seoul, KR;
Young-Hee Song, Yongin-si, KR;
Sung-min Sim, Seongnam-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
Provided is a method for manufacturing WLCSP devices that includes preparing at least two wafers, each wafer having a plurality of corresponding semiconductor chips, each semiconductor chip having through electrodes formed in the peripheral surface region, forming or applying a solid adhesive region to a central surface region, stacking a plurality of wafers and attaching corresponding chips provided on adjacent wafers with the solid adhesive region and connecting corresponding through electrodes of adjacent semiconductor chips, dividing the stacked wafers into individual chip stack packages, and injecting a liquid adhesive into a space remaining between adjacent semiconductor chips incorporated in the resulting chip stack package. By reducing the likelihood of void regions between adjacent semiconductor chips, it is expected that a method according to the exemplary embodiments of the present invention exhibit improved mechanical stability and reliability.