The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2006

Filed:

Mar. 24, 2004
Applicants:

Haowen Bu, Plano, TX (US);

Jiong-ping LU, Richardson, TX (US);

Shaofeng Yu, Plano, TX (US);

Ping Jiang, Plano, TX (US);

Clint Montgomery, Coppell, TX (US);

Inventors:

Haowen Bu, Plano, TX (US);

Jiong-Ping Lu, Richardson, TX (US);

Shaofeng Yu, Plano, TX (US);

Ping Jiang, Plano, TX (US);

Clint Montgomery, Coppell, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/4763 (2006.01); H01L 21/461 (2006.01); H01L 21/302 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (), among other possible elements, includes a silicided gate electrode () located over a substrate (), the silicided gate electrode () having gate sidewall spacers () located on sidewalls thereof. The semiconductor device () further includes source/drain regions () located in the substrate () proximate the silicided gate electrode (), and silicided source/drain regions () located in the source/drain regions () and at least partially under the gate sidewall spacers ().


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