The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2006
Filed:
Jul. 23, 2003
Harry D. Cox, Rifton, NY (US);
David P. Daniel, Burlington, VT (US);
Leonard J. Gardecki, Essex, VT (US);
Albert J. Gregoritsch, Iii, Jericho, VT (US);
Ruth A. Machell Julianelle, Underhill, VT (US);
Charles H. Keeler, Essex Junction, VT (US);
Doris P. Pulaski, Holmes, NY (US);
Mary A. Schaffer, Hopewell Junction, NY (US);
David L. Smith, Pleasant Valley, NY (US);
David J. Specht, Duxbury, VT (US);
Adolf E. Wirsing, South Hero, VT (US);
Harry D. Cox, Rifton, NY (US);
David P. Daniel, Burlington, VT (US);
Leonard J. Gardecki, Essex, VT (US);
Albert J. Gregoritsch, III, Jericho, VT (US);
Ruth A. Machell Julianelle, Underhill, VT (US);
Charles H. Keeler, Essex Junction, VT (US);
Doris P. Pulaski, Holmes, NY (US);
Mary A. Schaffer, Hopewell Junction, NY (US);
David L. Smith, Pleasant Valley, NY (US);
David J. Specht, Duxbury, VT (US);
Adolf E. Wirsing, South Hero, VT (US);
International Business Machines Corp., Armonk, NY (US);
Abstract
A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.