The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2006

Filed:

Jun. 24, 2005
Applicants:

Suman Datta, Beaverton, OR (US);

Brian S. Doyle, Portland, OR (US);

Robert S. Chau, Beaverton, OR (US);

Jack Kavalieros, Portland, OR (US);

BO Zheng, Beaverton, OR (US);

Scott A. Hareland, Tigard, OR (US);

Inventors:

Suman Datta, Beaverton, OR (US);

Brian S. Doyle, Portland, OR (US);

Robert S. Chau, Beaverton, OR (US);

Jack Kavalieros, Portland, OR (US);

Bo Zheng, Beaverton, OR (US);

Scott A. Hareland, Tigard, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.


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