The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2006
Filed:
Mar. 30, 2005
Yi-cheng Liu, Taipei, TW;
Wen-chi Chen, Chang-Hua Hsien, TW;
Tzu-yun Chang, Hsin-Chu Hsien, TW;
Bang-chiang Lan, Taipei, TW;
Cheng-tung Huang, Kao-Hsiung, TW;
Wei-tsun Shiau, Kao-Hsiung Hsien, TW;
Kuan-yang Liao, Taipei, TW;
Yi-Cheng Liu, Taipei, TW;
Wen-Chi Chen, Chang-Hua Hsien, TW;
Tzu-Yun Chang, Hsin-Chu Hsien, TW;
Bang-Chiang Lan, Taipei, TW;
Cheng-Tung Huang, Kao-Hsiung, TW;
Wei-Tsun Shiau, Kao-Hsiung Hsien, TW;
Kuan-Yang Liao, Taipei, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.