The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2006
Filed:
Apr. 24, 2006
Sheng Feng, Cupertino, CA (US);
Tong Liu, San Jose, CA (US);
Jung-cheun Lien, San Jose, CA (US);
Actel Corporation, Mountain View, CA (US);
Abstract
An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each file comprises a plurality of functional and interface groups and a primary routing structure, which is coupled to the functional and interface groups and is configured to receive and route primary output signals within at least one FPGA tile, and provide primary input signals to the functional and interface groups. Each functional group is configured to receive input signals, perform logic operations, and generate output signals and is configured to transfer signals from the routing structure to outside of at least one FPGA file, and includes a plurality of input multiplexers configured to select signals received from outside at least one FPGA tile and provide signals to the routing structure inside at least one FPGA tile.