Controllable conduction device with electrostatic barrier

Abstract

A controllable conduction device in the form of a transistor comprises source and drain regionsbetween which extends a conduction path P for charge carriers, a gatefor controlling charge carrier flow along the conduction path and a multiple layer structureproviding a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.