The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2006
Filed:
Sep. 26, 2003
Michael E. Johnson, Tempe, AZ (US);
Peter Elenius, Scottsdale, AZ (US);
Deok Hoon Kim, Tempe, AZ (US);
Michael E. Johnson, Tempe, AZ (US);
Peter Elenius, Scottsdale, AZ (US);
Deok Hoon Kim, Tempe, AZ (US);
FlipChip International LLC, Phoenix, AZ (US);
Abstract
A wafer-level CSP () includes at least one die () from a wafer. The wafer-level CSP has a plurality of solder ball pads (), a solder ball () at each solder ball pad and a polymer collar () around each solder ball. A moat () is formed in the surface of a polymer layer () disposed on the wafer during manufacturing of the wafer-level CSP. A temporarily liquified residual () from the polymer collar, which occurs while the wafer is heated to the reflow temperature of the solder ball, flows from the polymer collar. The moat acts as a barrier to material flow, limiting the distance that the residual spreads while liquified. The residual from the polymer collar remains within a region () defined by the moat. A full-depth moat () extends completely through the polymer layer. Alternatively, a partial-depth moat (and) extends partially through the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).