The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2006

Filed:

Aug. 09, 2004
Applicants:

John Barnak, Beaverton, OR (US);

Collin Borla, Sherwood, OR (US);

Mark Doczy, Beaverton, OR (US);

Markus Kuhn, Hillsboro, OR (US);

Jacob M. Jensen, Springfield, OR (US);

Inventors:

John Barnak, Beaverton, OR (US);

Collin Borla, Sherwood, OR (US);

Mark Doczy, Beaverton, OR (US);

Markus Kuhn, Hillsboro, OR (US);

Jacob M. Jensen, Springfield, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2006.01); H02L 31/113 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or 'tuned' depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.


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