The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2006
Filed:
Dec. 10, 2004
Biju Chandran, Chandler, AZ (US);
Carlos A. Gonzalez, Chandler, AZ (US);
Biju Chandran, Chandler, AZ (US);
Carlos A. Gonzalez, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A low resistance package-to-die interconnect scheme for reduced die stresses includes a relatively low melting temperature and yield strength solder on the die and a relatively higher melting temperature and electrically conductive material such as copper on the substrate. A soldered joint connects the solder to the electrically conductive material to couple/connect the die and substrate to one another. The soldered joint is formed by heating the die and solder thereon to at least the melting temperature of the solder and thereafter contacting the molten solder with the conductive material on the substrate, which is at a substantially lower temperature for minimizing residual stress from soldering due to coefficient of thermal expansion mismatch between the substrate and die.