Multi-layer reducible sidewall process

Abstract

The present invention pertains to a multi-layer sidewall process () that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed () alongside a gate structure of a transistor to facilitate implanting source/drain dopants far enough away from the gate structure so that dopant atoms are unlikely to migrate into a channel area under the gate structure. Additionally, the process provides uniform layers for dopant atoms to pass through to mitigate variations in device characteristics across a wafer. The manner of forming the sidewall spacers also allows a salicide blocking process to be simplified. The first sidewall spacers are subsequently reduced () to establish second sidewall spacers having second widths which are smaller than the first widths. The smaller second sidewall spacers facilitate compliance with design rules by allowing source and drain contacts to be formed closer to the gate structure.