The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2006

Filed:

Feb. 17, 2004
Applicants:

Seong-jun Heo, Seoul, KR;

Sun-pil Youn, Seoul, KR;

Sung-man Kim, Gyeonggi-do, KR;

Si-young Choi, Gyeonggi-do, KR;

Gil-heyun Choi, Gyeonggi-do, KR;

Ja-hum Ku, Gyeonggi-do, KR;

Chang-won Lee, Gyeonggi-do, KR;

Jong-myeong Lee, Gyeonggi-do, KR;

Kwon-sun Ryu, Gyeonggi-do, KR;

Inventors:

Seong-Jun Heo, Seoul, KR;

Sun-Pil Youn, Seoul, KR;

Sung-Man Kim, Gyeonggi-do, KR;

Si-Young Choi, Gyeonggi-do, KR;

Gil-Heyun Choi, Gyeonggi-do, KR;

Ja-Hum Ku, Gyeonggi-do, KR;

Chang-Won Lee, Gyeonggi-do, KR;

Jong-Myeong Lee, Gyeonggi-do, KR;

Kwon-Sun Ryu, Gyeonggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.


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